With the recent increasing trend of power consumption by processor, the power consumption has been suppressed generally by lowering the source voltage. It has been known that lowering of the voltage is feasible for the logic section of the processor (0.3 V, for example), but difficult for the memory section such as cache (0.7 V, for example). Accordingly, the cache which stores commands and data has been understood as a bottleneck in achieving the low power consumption.
An exemplary system for reducing power consumption in an electronic circuit is described in Patent Document 1 (Japanese Laid-Open Patent Publication No. H10-124202). In the system described in Patent Document 1 illustrated in FIG. 11, a cache 50 designed to lower the power consumption has two small-area caches 52, 53 typically composed of memory elements such as SRAM (Static Random Access Memory), and a cache control unit 40 for controlling the cache. An essential feature of this technique resides in achieving the low power consumption, by interrupting power supply to the small-area cache 53. In other words, the low power consumption is implemented by reducing the area used for the operation.
On the other hand, in a semiconductor device described in Patent Document 2 (Japanese Laid-Open Patent Publication No. 2008-47190), a cache memory in a chip is configured by L1 cache SRAMs each having a relatively small capacity, and L2 cache SRAMs each having a relatively large capacity, the power consumption of which is suppressed by appropriately switching between the L1 and L2 cache SRAMs while controlling the increase of the size of the chip.